The invention concerns a multilevel convertor for connection to an AC system, and in particular, but not exclusively, a multilevel convertor for use as a static VAr (volt-amp reactive) compensator.
Multilevel convertors are known for fulfilling various functions, one function being the drawing of adjustable lagging or leading reactive power from an AC system to which they are connected. The aim in such an process may be to stabilise some parameter of AC system operation, such as, for example, the level of AC voltage existing on the AC system. One type of multilevel convertor is shown in FIG. 1. In FIG. 1, a multilevel convertor 10, which is applied for use as a static VAr compensator (SVC), consists of a set of capacitors 20 connected in series, and a likewise series-connected set of switching devices 30, which are assumed to be, typically, gate-turn-off thyristors (GTO's). The set of GTO's 30 is connected in parallel with the set of capacitors 20, the tapping points of the GTO's being connected via a set of diodes 40 to respective tapping points of the set of capacitors 20. The convertor 10 is connected to a three-phase AC system 50 through a three-phase transformer 48. The AC system is represented in simplified form as a three-phase Thevenin-equivalent source generator 51 and impedance 52 feeding three-phase busbars 53. To accommodate the three phases, the set of GTO's 30 are triplicated at 30' and 30", the tapping points of these latter two sets being taken by way of diode sets 40' and 40" (not shown) to the respective tapping points of the set of capacitors 20. Thus, the same set of capacitors is shared by all three phases.
A control system 60, which in normal operation is synchronised with the AC system frequency, sets up the required drive signals for the GTO sets 30, 30' and 30" on lines 61. In operation, the control system 60 switches groups of GTO's 30, 30', 30" on and off in a given sequence, so as to connect each transformer secondary terminal to the nodes D to H of the set of capacitors 20 in turn. It is assumed to begin with that the capacitors 21-24 are all charged to a certain DC voltage level. Thus, when the GTO's are switched in the correct sequence, a pseudo-sinusoidal voltage whose waveform consists of a number of steps, in this case five, is imposed on the AC system 50 via the transformer 48. The control system 60 is arranged so that, in normal operation, the multilevel voltage appearing on each of nodes A, B and C for the three phases is in phase with the AC system voltage, the amplitude of the multilevel voltage being a function of the amount of DC charge on the capacitors 20. Since, now, the transformer linking the convertor 10 and the AC system 50 appears as a leakage inductance connected between them, the currents i.sub.A, i.sub.B and i.sub.C will be reactive current and the convertor will appear either as a leading (capacitive) reactive power source or as a lagging (inductive) reactive power source to the AC system, depending on whether the multilevel voltage on nodes A, B and C has a higher or lower amplitude than the AC system voltage on the busbars 53. This may be used to increase or decrease, respectively, the voltage level of the AC system busbars 53, or alternatively maintain this voltage constant by compensating for the effects of real and reactive current changes in loads (not shown) connected to the busbars.
Waveforms for the various voltages and currents in the multilevel circuit are shown in FIG. 2. The period of the AC system voltage, which is assumed to be sinusoidal, is divided into eight segments for the five-level convertor illustrated in FIG. 1. The GTO's are arranged by the control system 60 to conduct at the times t.sub.1 -t.sub.2, t.sub.2 -t.sub.3, etc, so that at each successive time segment successive nodes D-H of the set of capacitors 20 are coupled to node A, in the case of the first phase, and to nodes B and C in the case of the second and third phases, respectively. The switching sequence is shown in Table 1 below:
______________________________________ References of Phase A voltage GTO's nominally (connection refer- Time conducting ence) ______________________________________ t.sub.1 -t.sub.2 33, 34, 35, 36 F t.sub.2 -t.sub.3 32, 33, 34, 35 E t.sub.3 -t.sub.4 31, 32, 33, 34 D t.sub.4 -t.sub.5 32, 33, 34, 35 E t.sub.5 -t.sub.6 33, 34, 35, 36 F t.sub.6 -t.sub.7 34, 35, 36, 37 G t.sub.7 -t.sub.8 35, 36, 37, 38 H t.sub.8 -t.sub.9 34, 35, 36, 37 G ______________________________________
This sequence recurs for each successive cycle of the AC system voltage, and assumes operation under either steady-state conditions, e.g. a constant busbar voltage, or in changing conditions.
The current in any conducting GTO 31-38 or diode 31A-38A or 41-46 at any instant is the AC phase current i.sub.A, which may be positive or negative, depending on the operating conditions of the SVC. Thus, taking time interval t.sub.1 -t.sub.2 as an example, if phase current i.sub.A is positive (i.e. in the direction of the arrow shown in FIG. 1) its current path will be GTO's 35 and 36 and diode 44. If it is negative, its path will be diode 43 and GTO's 33 and 34. In either case, the phase voltage v.sub.A will be substantially the voltage on node F, as given in the above Table, neglecting the small voltage drops in the conducting GTO's or diodes. For other time periods, the phase voltage will be similarly clamped to node E, D, G or H. The waveform v.sub.A in FIG. 2 is shown taken with respect to node F, which may be a purely fictitious neutral connection.
The waveform v.sub.A can be seen to have five voltage levels corresponding to the five nodes in the set of capacitors 20, i.e. the convertor of FIG. 1 is said to be a "five-level" convertor. The stepped waveform will normally be arranged to be a reasonably close approximation to a sine wave in order to miniraise the imposition of harmonics onto the AC system. The resulting phase current i.sub.A is therefore assumed to be substantially sinusoidal, as illustrated in FIG. 2, and is a function of the difference between the AC busbar voltage (not shown), the phase voltage v.sub.A and the leakage reactance of the transformer 48.
The same basic operation obtains also for the other two phases, B and C, so that similar phase-current and phase-voltage waveforms occur for these phases also, but separated from the phase A waveforms by 120.degree. and 240.degree. electrical, respectively.
The various voltages and currents pertaining to the set of capacitors 20 are shown in FIG. 3. The currents are divided into, firstly, capacitor "tap currents", i.sub.D -i.sub.H, which represent the currents flowing into or out of the tapping points (nodes) of the capacitor set 20, and secondly, the series currents, i.sub.21 -i.sub.24, which represent the currents through each capacitor 21-24 in turn. The DC potentials already existing on the capacitors 21-24 are shown as V.sub.21 -V.sub.24, respectively. The action of the GTO switching is shown carried out by an equivalent multi-way switch 39, the phase voltage being considered as the voltage that exists between the common terminal of the switch 39 ("A") and the mid-point "neutral" (N) of the set of capacitors.
The waveforms of the capacitor "tap" currents and series currents are shown in FIG. 2, under i.sub.D -i.sub.F and i.sub.21 - i.sub.24, respectively. Current i.sub.D is the tap current flowing into node D during time period t.sub.3 -t.sub.4, i.sub.E is the tap current flowing into node E during time periods t.sub.2 -t.sub.3 and t.sub.4 -t.sub.5, and so on. The series current i.sub.21 is the same as the tap current i.sub.D, series current i.sub.22 equals tap currents i.sub.D +i.sub.E, and so on. The mean voltage across each capacitor is the DC voltage that is imposed on the capacitors at the start of operation, this being effected, for example, by arranging for the control system 60 to switch the GTO's such that the capacitors charge up to an initial DC value from the AC system when the SVC is first switched on. Since there can be no mean current flowing through a capacitor in steady state, only "displacement" current, the waveforms i.sub.D -i.sub.H and i.sub.21 -i.sub.24 are shown as having zero mean current. The capacitor voltages V.sub.21 -V.sub.24 will, of course, not be totally invariant even under steady-state conditions, since they will have the currents i.sub.21 -i.sub.24 flowing through them, but the average voltage across each capacitor will be that to which it is initially charged.
Assuming now that the SVC is arranged to hold, say, the voltage of the AC system substantially constant, the control system 60 will react to any change in that voltage by causing the rate at which the GTO's are switched to be either accelerated or retarded, depending on whether the AC system voltage has decreased or increased. Such a change in the rate of switching has the effect of moving the phase voltage v.sub.A (and v.sub.B and v.sub.C) out of phase with the AC system voltage and creating a real component in the corresponding phase current. This real component causes a temporary flow of real power into or out of, as the case may be, the convertor, which causes a corresponding increase or decrease in the mean DC charge on the capacitors. This, in turn, increases or decreases the phase voltage accordingly, thereby compensating for the original disturbance in the AC system voltage. Thereafter, phase voltage returns to an in-phase relationship with the AC system voltage. Thus, it can be seen that the synchronism that normally exists between phase voltage and AC system voltage is momentarily disturbed when a change in the latter occurs, in order to correct for this change, but is restored immediately correction has been effected.
In practice, the kind of multilevel convertor arrangement described above has been found to have a drawback, namely a form of internal instability in which the relative DC voltages on the capacitors deviate to assume steady-state values grossly in error from the ideal "designed" values. Such gross errors may occur spontaneously, or due to large transients, for example during recovery after temporary AC system short-circuits. The result is that the phase voltages v.sub.A, v.sub.B and v.sub.C are distorted, together with the corresponding phase currents, and excessive harmonic distortion is caused in the AC system. Further, since the peak voltages across the GTO's and diodes are dependent on the voltages on the capacitors, these semiconductor devices (and also the capacitors themselves) may be subjected to excess voltages, resulting in device failure.
It would be desirable to provide a multilevel convertor which mitigates the disadvantages associated with the known multilevel convertor arrangements.